Fullstack Job: ML Compiler Intern

About us

d-Matrix is developing a novel hardware system and a full-stack software solution to accelerate large-scale modern deep neural network compute workloads for the cloud. Leveraging a combination of unique in-memory compute array design, digital signal processing system design, and on-chip and chip-to-chip interconnect fabric, d-Matrix's AI compute engine holds the promise of drastically improving power-efficiency and compute latency of cloud inference workloads, by orders of magnitude compared to competition.

Why d-Matrix

We want to build a company and a culture that sustains the tests of time. We offer the candidate a very unique opportunity to express themselves and become a future leader in an industry that will have a huge influence globally. We are striving to build a culture of transparency, inclusiveness and intellectual honesty while ensuring all our team members are always learning and having fun on the journey. We have built the industry’s first highly programmable in-memory computing architecture that applies to a broad class of applications from cloud to edge. The candidate will get to work on a path breaking architecture with a highly experienced team that knows what it takes to build a successful business.

The role: ML Compiler Intern

The Compiler Backend Team at d-Matrix is responsible for developing the software that performs the logical-to-physical mapping of a graph expressed in an IR dialect (like Tensor Operator Set Architecture (TOSA), MHLO or Linalg) to the physical architecture of the distributed parallel memory accelerator used to execute it. It performs multiple passes over the IR to apply operations like tiling, compute resource allocation, memory buffer allocation, scheduling and code generation. You will be joining a team of exceptional people enthusiastic about developing state-of-the-art ML compiler technology. This internship position is for 3 months.

In this role you will design, implement and evaluate a method for managing floating point data types in the compiler. You will work under the guidance of two members of the compiler backend team. One, is an experienced compiler developer based in the West Coast of the US.

You will engage and collaborate with engineering team in the US to understand the mechanisms made available by the hardware design to perform efficient floating point operations using reduced precision floating point data types.

Successful completion of the project will be demonstrated by a simple model output by the compiler incorporating the your code that executes correctly on the hardware instruction set architecture (ISA) simulator. This model incorporates various number format representations for reduced precision floating point.

Qualifications